Appendix: Debugging

For each benchmark, the ISA simulator prints an instruction trace to benchmarks/*.riscv.out.

The disassembly for specific benchmarks can be dumped as follows, which can be useful for comparing against the instruction traces and verifying that the code was assembled as expected.

cd benchmarks
make <bmark>.riscv.dump

It is also possible to generate a more detailed commit log that records every value written to each destination register and the address stream of memory accesses.

make <bmark>.riscv.log

The current SEW, LMUL, and vector length are also logged for each vector instruction. Note that the contents of a vector register are shown concatenated as a single raw hex value; refer to the “(https://inst.eecs.berkeley.edu/~cs152/sp22/handouts/sp22/riscv-v-spec-0.10.html#_mapping_of_vector_elements_to_vector_register_state)” section in the RVV spec for how to unpack the layout. For $\texttt{LMUL} > 1$, the v registers that comprise a vector register group are displayed separately, possibly in an arbitrary order.

Finally, it can be very helpful to debug using a smaller dataset. Switch to dataset2.h for the open-ended problems, or generate custom input data using the provided scripts. However, make sure that your code eventually passes the test using dataset1.h.